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| SI5332 data sheet 6/8/12-output any-frequency clock generator based on silicon labs proprietary multisynth ? flexible frequency synthesis technology, the SI5332 generates any combination of output frequencies with excellent jitter perfor- mance (230 fs rms). the device's highly flexible architecture enables a single device to generate a wide range of integer and non-integer related frequencies on up to 12 differ- ential clock outputs with 0 ppm frequency synthesis error. the device offers multiple banks of outputs that can each be tied to independent voltages, enabling usage in mixed-supply applications. further, the signal format of each clock output is user-config- urable. given its frequency, format, and supply voltage flexibility, the SI5332 is ideally suited to replace multiple clock ics and oscillators with a single device. the SI5332 is quickly and easily configured using clockbuilder pro ? software. clock- builder pro assigns a custom part number for each unique configuration. devices ordered with custom part numbers are factory-programmed free of charge, making it easy to get a custom clock uniquely tailored for each application. SI5332 can also be programmed via an i2c serial interface. applications: ? servers, storage, search acceleration ? ethernet switches, routers ? small cells, mobile backhaul/fronthaul ? print imaging ? communications ? broadcast video ? test and measurement ? industrial, embedded computing key features ? any-frequency 6/8/12-output programmable clock generators ? offered in three different package sizes, supporting different combinations of output clocks and user configurable hardware input pins ? 32-pin qfn, up to 6 outputs ? 40-pin qfn, up to 8 outputs ? 48-pin qfn, up to 12 outputs ? multisynth technology enables any- frequency synthesis on any output up to 250 mhz ? highly configurable output path featuring a cross point mux ? up to three independent fractional synthesis output paths ? up to five independent integer dividers ? embedded 50 mhz crystal option ? input frequency range: ? external crystal: 16 to 50 mhz ? differential clock: 10 to 250 mhz ? lvcmos clock: 10 to 170 mhz ? output frequency range: ? differential: 5 to 312.5 mhz ? lvcmos: 5 to 170 mhz ? user-configurable clock output signal format per output: lvds, lvpecl, hcsl, lvcmos ? temperature range: C40 to +85 c ? down and center spread spectrum ? pb-free, rohs-6 compliant ? SI5332 family reference manual silabs.com | building a more connected world. rev. 0.7
table of contents 1. features list ............................... 4 2. ordering guide ..............................5 3. functional description ............................6 3.1 functional block diagrams .........................7 3.2 modes of operation ............................9 3.2.1 initialization ............................9 3.3 frequency configuration ..........................9 3.4 inputs ................................ 10 3.4.1 external reference input (xa/xb) ..................... 10 3.4.2 input clocks ............................ 10 3.4.3 input selection ........................... 10 3.5 outputs ................................ 11 3.5.1 output signal format ......................... 11 3.5.2 differential output terminations ...................... 12 3.5.3 lvcmos output terminations ...................... 16 3.5.4 lvcmos output signal swing ...................... 16 3.5.5 lvcmos output polarity ........................ 16 3.5.6 lvcmos output configurable tr/tf .................... 16 3.5.7 output enable/disable ......................... 16 3.5.8 differential output configurable skew settings ................. 16 3.5.9 output driver state when disabled .................... 17 3.5.10 synchronous output disable feature ................... 17 3.6 spread spectrum ............................. 17 3.7 universal hardware input pins ........................ 18 3.8 custom factory pre-programmed parts ..................... 19 3.9 i2c serial interface ............................ 19 3.10 in-circuit programming .......................... 19 4. register map .............................. 20 5. electrical specifications .......................... 21 6. pin descriptions ............................. 35 6.1 pin descriptions (48-qfn) ......................... 35 6.2 pin descriptions (40-qfn) ......................... 40 6.3 pin descriptions (32-qfn) ......................... 44 7. package outline ............................. 48 7.1 SI5332 6x6 mm 48-qfn package diagram, external crystal versions (SI5332a/b/c/d) ..... 48 7.2 SI5332 6x6 mm 40-qfn package diagram, external crystal versions (SI5332a/b/c/d) ..... 49 7.3 SI5332 5x5 mm 32-qfn package diagram, external crystal versions (SI5332a/b/c/d) ..... 50 7.4 SI5332 6x6 mm 48-qfn package diagram, embedded crystal versions (SI5332e/f/g/h) .... 51 silabs.com | building a more connected world. rev. 0.7 | 2 7.5 SI5332 6x6 mm 40-qfn package diagram, embedded crystal versions (SI5332e/f/g/h) .... 52 7.6 SI5332 5x5 mm 32-qfn package diagram, embedded crystal versions (SI5332e/f/g/h) .... 53 8. pcb land pattern ............................ 54 8.1 SI5332 48-qfn land pattern ......................... 54 8.2 SI5332 40-qfn land pattern ......................... 55 8.3 SI5332 32-qfn land pattern ......................... 56 9. top marking ............................... 57 10. document change list .......................... 58 10.1 revision 0.7 .............................. 58 silabs.com | building a more connected world. rev. 0.7 | 3 1. features list ? any-frequency 6/8/12-output programmable clock generators ? offered in three different package sizes, supporting different combinations of output clocks and user configurable hardware input pins ? 32-pin qfn, up to 6 outputs ? 40-pin qfn, up to 8 outputs ? 48-pin qfn, up to 12 outputs ? multisynth ? technology enables any-frequency synthesis on any output up to 250 mhz ? embedded 50 mhz crystal option ? highly configurable output path featuring a cross point mux ? up to three independent fractional synthesis output paths ? up to five independent integer dividers ? ordering options for embedded 50 mhz reference crystal ? input frequency range: ? external crystal: 16 to 50 mhz ? differential clock: 10 to 250 mhz ? lvcmos clock: 10 to 170 mhz ? output frequency range: ? differential: 5 to 312.5 mhz ? lvcmos: 5 to 170 mhz ? embedded crystal option on 8-output and 12-output devices. ? user-configurable clock output signal format per output: lvds, lvpecl, hcsl, lvcmos ? low phase jitter: 230 fs rms ? pcie gen1/2/3/4, sris compliant ? 1.8 v, 2.5 v, 3.3 v core vdd ? adjustable output-output delay ? independent glitchless on-the-fly output frequency changes ? very low power consumption ? independent output supply pins for each bank of outputs: ? 1.8 v, 2.5 v, or 3.3 v differential ? 1.5 v, 1.8 v, 2.5 v, 3.3 v lvcmos ? programmable spread spectrum ? down and center spread from C0.1% C2.5% in 0.01% steps at 30 to 33 khz ? integrated power supply filtering ? serial interface: i 2 c ? clockbuilder pro software utility simplifies device configuration and assigns custom part numbers ? temperature range: C40 to +85 c ? pb-free, rohs-6 compliant SI5332 data sheet features list silabs.com | building a more connected world. rev. 0.7 | 4 2. ordering guide SI5332x cxxxxx - gmpr f p b m dp r m f mp m p d & * 0 4 ) 1 5 2 + 6 3 e i u h h 3 i r u r x w s x w s l q 4 ) 1 i r u r x w s x w s l q 4 ) 1 i r u r x w s x w s l q 4 ) 1 5 7 d s h 5 h h o r u g h u l q j r s w l r q ordering part number input type output clock frequency range operating temperature range SI5332a 5mhz - 312.5mhz SI5332b 5mhz - 200mhz SI5332c 5mhz - 312.5mhz SI5332d 5mhz - 200mhz SI5332e 5mhz - 312.5mhz SI5332f 5mhz - 200mhz SI5332g 5mhz - 312.5mhz SI5332h 5mhz - 200mhz -40 to +85c integer and fractional mode embedded crystal or external clock integer and fractional mode integer mode only integer mode only frequency synthesis mode integer and fractional mode external crystal or clock integer and fractional mode integer mode only integer mode only f p mp m p d & * 0 4 ) 1 5 2 + 6 3 e i u h h s i r u r x w s x w s l q 4 ) 1 i r u r x w s x w s l q 4 ) 1 i r u r x w s x w s l q 4 ) 1 5 7 d s h 5 h h o r u g h u l q j r s w l r q ordering part number input type output clock frequency range operating temperature range SI5332a 5mhz - 312.5mhz SI5332b 5mhz - 200mhz SI5332c 5mhz - 312.5mhz SI5332d 5mhz - 200mhz SI5332e 5mhz - 312.5mhz SI5332f 5mhz - 200mhz SI5332g 5mhz - 312.5mhz SI5332h 5mhz - 200mhz -40 to +85c integer and fractional mode embedded crystal or external clock integer and fractional mode integer mode only integer mode only frequency synthesis mode integer and fractional mode external crystal or clock integer and fractional mode integer mode only integer mode only pre-programmed devices using a clockbuilder pro configuration file SI5332x - c - gmpr blank devices, in-system programmable p dccc p pmp imn po mpb p dccc p pmp imn po mpb figure 2.1. orderable part number guide SI5332 data sheet ordering guide silabs.com building a more connected world. rev. 0.7 5 3. functional description the SI5332 is a high-performance, low-jitter clock generator capable of synthesizing up to twelve user-programmable clock frequencies up to 312.5 mhz. the device supports free run operation using an external or embedded crystal, or it can lock to an external clock signal. the output drivers support up to twelve differential clocks or twenty four lvcmos clocks, or a combination of both. the output drivers are configurable to support common signal formats, such as lvpecl, lvds, hcsl, and lvcmos. vddo pins are provided for versatility, which can be set to 3.3 v, 2.5 v, 1.8 v or 1.5 v (cmos only) to power the multi-format output drivers. the core voltage supply (vdd) accepts 3.3 v, 2.5 v, or 1.8 v and is independent from the output supplies (vddoxs). using its two-stage synthesis archi- tecture and patented high-resolution low-jitter multisynth technology, the SI5332 can generate an entire clock tree from a single device. the SI5332 combines a wideband pll with next generation multisynth technology to offer the industrys highest output count high per- formance programmable clock generator, while maintaining a jitter performance of 230 fs rms. the pll locks to either an external 16-50 mhz crystal or an embedded 50 mhz crystal for generating for generating free-running clocks or to an external clock (clkin_2/ clkin_2# or clkin_3/clkin_3#) for generating synchronous clocks. in free-run mode, the oscillator frequency is multiplied by the pll and then divided down either by an integer divider or multisynth for fractional synthesis. the SI5332 features user-defined universal hardware input pins which can be configured in the clockbuilder pro software utility. uni- versal hardware pins can be used for oe, spread spectrum enable, input clock selection, output frequency selection, or i2c address select. if additional hardware input pins are needed, a user can define a different clock output as universal hardware input pins instead using clockbuilder pro. the device provides the option of storing a user-defined clock configuration in its non-volatile memory (nvm), which becomes the de- fault clock configuration at power-up. to enable in-system programming, a power up mode is available through otp which powers up the chip in an otp defined default mode but with no outputs enabled. this allows a host processor to first write a user defined subset of the registers and then restart the power-up sequence to activate the newly programmed configuration without re-downloading the otp. SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 6 3.1 functional block diagrams SI5332: 12-output, 48-qfn multi synth multi synth int int int int nvm i2c sclk sdata hw input control input1 input2 input3 input4 input5 input6 input7 vddo4 out9 out9b int out10 vddo5 out10b int out11 out11b int bank d out0 vddo0 out0b int vddo2 out3 out3b int out4 out4b int out5 out5b int bank b out1 vddo1 out1b int out2 out2b int bank a vddo3 out6 out6b int out7 out7b int out8 out8b int bank c xtal osc SI5332a/b/c/d: external crystal SI5332e/f/g/h: internal crystal pll int clkin_3 clkin_3b clkin_2 clkin_2b int figure 3.1. block diagram for 12-output SI5332 in 48-qfn the SI5332 48-qfn features: ? up to twelve differential clock outputs, with six vddo pins. ? seven user-configurable hw input pins, defined using clockbuilder pro. SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 7 SI5332: 8-output, 40-qfn multi synth int multi synth int int int int out0 vddo0 vddo3 out4 out1 vddo1 out2 vddo2 out0b out4b out1b out2b int int int int nvm i2c sclk sdata pll vddo4 out6 out6b int vddo5 out7 out7b int out3 out3b int out5 out5b int hw input control input1 input2 input3 input4 input5 input6 input7 bank a bank b clkin_3 clkin_3b clkin_2 xtal osc clkin_2b SI5332a/b/c/d: external crystal SI5332e/f/g/h: internal crystal int figure 3.2. block diagram for 8-output SI5332 in 40-qfn the SI5332 40-qfn features: ? up to eight differential clock outputs, with six vddo pins. ? seven user-configurable hw input pins, defined using clockbuilder pro. SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 8 SI5332: 6-output, 32-qfn multi synth int multi synth int int int int out0 vddo0 vddo3 vddo4 vddo5 out3 out4 out5b out1 vddo1 out2 vddo2 out0b out3b out4b out5 out1b out2b int int int int int int nvm i2c hw input control sclk sdata input1 input2 input3 input4 input5 pll clkin_2 xtal osc clkin_2b SI5332a/b/c/d: external crystal SI5332e/f/g/h: internal crystal int figure 3.3. block diagram for 6-output SI5332 in 32-qfn the SI5332 32-qfn features: ? up to six differential clock outputs with individual vddo. ? five user-configurable hw input pins, defined using clockbuilder pro. 3.2 modes of operation the SI5332 supports both free-run and synchronous modes of operation. the default mode selection is set in clockbuilder pro. alterna- tively, a universal hardware input pin can be defined as clkin_sel to select between a crystal or clock input. there is also the option to select the input source via the serial interface by writing to the input select register. 3.2.1 initialization once power is applied, the device begins an initialization period where it downloads default register values and configuration data from nvm and performs other initialization tasks. communicating with the device through the serial interface is possible once this initializa- tion period is complete. the clock outputs will be squelched until the device initialization is done. 3.3 frequency configuration the phase-locked loop is fully integrated and does not require external loop filter components. its function is to phase lock to the selec- ted input and provide a common synchronous reference to the high-performance multisynth fractional or integer dividers. a cross point mux connects any of the multisynth divided frequencies or int divided frequencies to individual output drivers or banks of output drivers. additional output integer dividers provide further frequency division by an even integer from 1 to 63. the frequency con- figuration of the device is programmed by setting the input dividers (p), the pll feedback fractional divider (mn/md), the multisynth fractional dividers (nn/nd), and the output integer dividers (r). silicon labs clockbuilder pro configuration utility determines the opti- mum divider values for any desired input and output frequency plan SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 9 3.4 inputs the SI5332 requires an external 16C30 mhz crystal at its xin/xout pins or the embedded 50 mhz crystal to operate in free-run mode, or an external input clock (clkin_2/clkin_2# or clkin_3/clkin_3#) for synchronous operation. an external crystal is not required in synchronous mode. 3.4.1 external reference input (xa/xb) an external crystal (xtal) is used in combination with the internal oscillator (osc) on SI5332a/b/c/d to produce a low jitter reference for the pll when operating in the free-run mode. frequency offsets due to c l mismatch can be adjusted using the frequency adjust- ment feature which allows frequency adjustments of 1000 ppm. the SI5332 reference manual provides additional information on pcb layout recommendations for the crystal to ensure optimum jitter performance. refer to table 5.4 external crystal input specification on page 24 for crystal specifications. for free-running operation, the internal oscillator can operate from a low-frequency fundamental mode crystal (xtal) with a resonant frequency of 16 to 50 mhz. a crystal can easily be connected to pins xa and xb without external components, as shown in the figure below. a register bit will allow the device to use an internal loading capacitor (cl) with a typical value of 12 pf or bypass the internal cl and use external cl. alternatively, an external cl can be used along with the internal cl. osc to synthesis stage or output selectors xtal xa xb figure 3.4. external reference input (xa/xb) the SI5332e/f/g/h options feature an embedded 50 mhz reference crystal that is used in the free run mode. 3.4.2 input clocks an input clock is available to synchronize the pll when operating in synchronous mode. this input can be configured as lvpecl, lvds or hcsl differential, or lvcmos. the recommended input termination schemes are shown in the SI5332 family reference manual . differential signals must be ac coupled. the single-ended lvcmos input is internally ac coupled, and only needs to meet a minimum voltage swing that may not exceed a maximum vih or minimum vil. unused inputs can be disabled by register configuration. 3.4.3 input selection the active clock input is selected by register control, or by defining a universal hardware input pin as clkin_sel in clockbuilder pro. a register bit determines input selection as pin or register selectable. if a universal input pin is defined as clkin_sel, that pin is selec- ted by default and is internally pulled high so that the free-run mode is automatically selected when left unconnected. if there is no clock signal on the selected input, the device will not generate output clocks. in a typical application, the SI5332 reference input is configured immediately after power-up and initialization. if the device is switched to another input more than 1000 ppm offset from the initial input, the device must be recalibrated manually to the new frequency, tem- porarily turning off the clock outputs. after the vco is recalibrated, the device will resume producing clock outputs. if the selected inputs are within 1000 ppm, any phase error difference will propagate through the device at a rate determined by the pll bandwidth. hitless switching and phase build-out are not supported by the SI5332. SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 10 3.5 outputs the SI5332 supports up to 12 differential output drivers. each output can be independently configured as a differential pair or as dual lvcmos outputs. the 8-output and 12-output devices feature banks of outputs, with each bank sharing a common vddo. table 3.1. clock outputs package maximum outputs 32-qfn 6 differential, 12 lvcmos 40-qfn 8 differential, 16 lvcmos 48-qfn 12 differential, 24 lvcmos the output stage is different for each of the three versions of SI5332. ? the 6-output device features individual vddo pins for each clock output. each clock output can be sourced from multisynth0, multi- synth1, the input reference clock, or one of the five int dividers through the cross point mux. ? the 8-output device includes four clock outputs with dedicated vddo pins, each of which can be sourced from multisynth0, multi- synth1, the input reference clock, or one of the five int dividers through the cross point mux. the remaining four clock outputs are divided into bank a and bank b. each bank of outputs can be sourced from multisynth0, multisynth1, the input reference clock, or one of the five int dividers through the cross point mux. the outputs in each of the two banks share a common vddo pin. ? the 12-output device includes two clock outputs with dedicated vddo pins, each of which can be sourced from multisynth0, multi- synth1, the input reference clock, or one of the five int dividers through the cross point mux. the remaining ten clock outputs are divided into bank a, bank b, bank c, and bank d. each bank of outputs can be sourced from multisynth0, multisynth1, the input reference clock, or one of the five int dividers through the cross point mux. the outputs in each of the four banks share a common vddo pin. utilizing the reference clock enables a fan-out buffer function from an input clock source to any bank of outputs. individual output integer output dividers (r) allow the generation of additional synchronous frequencies. these integer dividers are con- figurable as divide by 1 (default) through 63. 3.5.1 output signal format the differential output swing and common mode voltage are both fully programmable and compatible with a wide variety of signal for- mats including hcsl, lvds and lvpecl. in addition to supporting differential signals, any of the outputs can be configured as lvcmos drivers, enabling the device to support both differential and single-ended clock outputs. output formats can be defined in clockbuilder pro or via the serial interface. SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 11 3.5.2 differential output terminations lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 and 132 . the actual value should be selected to match the differential impedance (z0) of the transmission line. a typical point-to-point lvds design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. the standard lvds termination schematic as shown in figure 3.5 standard lvds termination on page 12 can be used with either type of output structure. figure 3.6 optional lvds termination on page 12 , which can also be used with both output types, is an optional termina- tion with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50 pf. if using a non- standard termination, please contact silicon labs to confirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receivers amplitude and common-mode input range should be verified for compati- bility with the output. [5 5 [5 w figure 3.5. standard lvds termination [5 5 [5 w / figure 3.6. optional lvds termination termination for 3.3 v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recom- mended only as guidelines. the differential outputs generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 3.7 3.3 v lvpecl output termination, option 1 on page 13 and figure 3.8 3.3 v lvpecl output termination, option 2 on page 13 show two different layouts. other suitable clock layouts may exist, and it would be recommended that the board designers simulate to guar- antee compatibility across all printed circuit and clock component process variations. SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 12 3.3v 3.3v lvpecl zo=50? zo=50? r1 50? r2 50? + - input vcc-2v rtt rtt = 54? figure 3.7. 3.3 v lvpecl output termination, option 1 3.3v 3.3v lvpecl zo=50? zo=50? r1 84? r2 84? + - input r4 125? r3 125? 3.3v figure 3.8. 3.3 v lvpecl output termination, option 2 termination for 2.5 v lvpecl outputs figure 3.9 2.5 v lvpecl termination example, option 1 on page 14 and figure 3.10 2.5 v lvpecl termination example, option 2 on page 14 show examples of termination for the 2.5 v lvpecl driver option. these terminations are equivalent to terminating 50 to vddo C 2 v. for vddo = 2.5 v, the vddo C 2 v is very close to ground level. the r3 in figure 3.10 2.5 v lvpecl termination example, option 2 on page 14 can be optionally eliminated using the termination shown in figure 3.9 2.5 v lvpecl termination example, option 1 on page 14 . SI5332 data sheet functional description silabs.com building a more connected world. rev. 0.7 13 2.5v 2.5v 2.5v lvpecl dri v er zo=50 ohm zo=50 ohm r1 62.5 ohm r2 62.5 ohm + - input r4 250 ohm r3 250 ohm 2.5v rtt = 29.5 ohm figure 3.9. 2.5 v lvpecl termination example, option 1 2.5v 2.5v 2.5v lvpecl dri v er zo=50 ohm zo=50 ohm r1 50ohm r2 50ohm + - input r3 18ohm figure 3.10. 2.5 v lvpecl termination example, option 2 SI5332 data sheet functional description silabs.com building a more connected world. rev. 0.7 14 termination for hcsl outputs the SI5332 hcsl driver option integrated termination resistors to simplify interfacing to an hcsl receiver. the hcsl driver supports both 100 ? and 85 ? transmission line options. this configuration option may be specified using clockbuilder pro or via the device i2c interface. h h i/[ i/[ figure 3.11. hcsl internal termination mode h h i/[ w w figure 3.12. hcsl external termination mode SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 15 3.5.3 lvcmos output terminations lvcmos outputs are dc-coupled, as shown in the figure below. h h figure 3.13. lvcmos output termination example, option 1 h w h w w w figure 3.14. lvcmos output termination example, option 2 3.5.4 lvcmos output signal swing the signal swing (v ol /v oh ) of the lvcmos output drivers is set by the voltage on the vddo pin for the respective bank. 3.5.5 lvcmos output polarity when a driver is configured as an lvcmos output it generates a clock signal on both pins (outx and outxb). by default, the clock on the outxb pin is generated in phase with the clock on the outx pin. the polarity of these clocks is configurable enabling complimenta- ry clock generation and/or inverted polarity with respect to other output drivers. 3.5.6 lvcmos output configurable tr/tf the SI5332 has four settings to choose from for lvcmos outputs up to 66 mhz at 50 ? internal impedance drive a 5, 50 ? trace. this can be configured using the clockbuilder pro software utility, or through the i2c programming interface. output frequencies greater than 66 mhz must use the fastest setting. 3.5.7 output enable/disable the universal hardware input pins can be programmed with either active low or active high polarity, to operate as output enable (oeb), controlling one or more outputs. pin assignment is done using clockbuilder pro. an output enable pin provides a convenient method of disabling or enabling the output drivers. when the output enable pin is held high all designated outputs will be disabled. when held low, the designated outputs will be enabled. outputs in the enabled state can be individually disabled through register control. 3.5.8 differential output configurable skew settings skew on the differential outputs can be independently configured. the skew is adjustable in 35 ps steps across a range of 280 ps. SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 16 3.5.9 output driver state when disabled the disabled state of an output driver is configurable as: disable low, disable high, or disable high-impedance. 3.5.10 synchronous output disable feature output clocks are always enabled and disabled synchronously. the output will wait until a clock period has completed before the driver is disabled. this prevents unwanted runt pulses from occurring when disabling an output. 3.6 spread spectrum to help reduce electromagnetic interference (emi), the SI5332 supports spread spectrum modulation. the output clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system emi. the SI5332 implements spread spectrum using its patented multisynth technology to achieve previously unattainable precision in both modulation rate and spreading magnitude. spread spectrum can be enabled through i2c, or by configuring one of the universal hardware input pins using clockbuilder pro. the SI5332 features both center and down spread spectrum modulation capability, from 0.1% to 2.5%. each multisynth is capable of generating an independent spread spectrum clock. the feature is enabled using a user-defined universal hardware input pin or via the device i2c interface. spread spectrum can be applied to any output clock, with any clock frequency up to 250 mhz. since the spread spectrum clock generation is performed in the multisynth fractional dividers, the spread spectrum waveform is highly consistent across process, voltage and temperature. the SI5332 features two independent multisynth dividers, enabling the device to provide two inde- pendent spread profiles simultaneously to the clock output banks. spread spectrum is commonly used for 100 mhz pci express clock outputs. to comply with the spread spectrum specifications for pci express, the spreading frequency should be set to a maximum of 33 khz and C0.5% down spread. a universal hardware input pin can be configured to toggle spread spectrum on/off. SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 17 3.7 universal hardware input pins universal hardware input pins are user configurable control input pins that can have one or more of the functions listed below assigned to them using clockbuilder pro. if more hardware input pins are needed, the differential input pins can be alternatively configured as two universal hardware input pins. contact silicon labs for further details. universal hardware input pins can be utilized for the following functions: table 3.2. universal hardware input pins description function spread_en0 spread spectrum enable on multisynth0 (n0). spread_en1 spread spectrum enable on multisynth0 (n1). fs_intx used to switch an integer output divider frequency from frequency a to frequency b. fs_msx used to switch a multisynth output divider output from frequency and/or change spread spectrum profile. oe output enable for one or more outputs. i2c address select sets the lsb of the i2c address to either 0 or 1. clkin_sel[1:0] selects between crystal or clock inputs. multisynth spread enable pins spread_en[1:0] pins are active pins that enable/disable spread spectrum on all outputs that correspond to mutlisynth0 or multisynth1, respectively. the change in frequency or spread spectrum will be instantaneous and may not be glitch free. table 3.3. spread_en pin selection table spread_enx 0 spread spectrum disabled on multisynthx 1 spread spectrum enabled on multisynthx output frequency select pins there are five integer dividers, one corresponding to each of the five output banks. using clockbuilder pro, a universal hardware input pin can be assigned for each integer divider, providing capability to select between two different pre-programmed divide values. divider values of every integer from 8 to 255 are available in clockbuilder pro for each integer divider. table 3.4. f s_int pin selection table f s_intx output frequency from intx 0 frequency a, as defined in clockbuilder pro 1 frequency b, as defined in clockbuilder pro SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 18 output enable a universal hardware input pin can be defined to control output enable of a differential output, a bank of differential outputs, or as a global output enable pin controlling all outputs. upon de-assertion of an oe pin, the corresponding output will be disabled within 2-6 clock cycles. asserting an oe pin from disable to enable will take <20 s for the output to have a clean clock. oe pins have program- mable 100 k? pull-up/pull-down or no pull resistors setting the disable state is programmable as 0, 1, hi-z, or free running. see the SI5332 family reference manual for details. output enabled/disabled for lvcmos are done in pairs. each differential buffer true and compliment output can generate an lvcmos clock and the oe pin associated with the true and compliment output buffer will control the respective lvcmos pair. for example: if diff0 is configured to be se1 and diff0# is configured to be se2 and oe1 is the associated oe pin, de-asserting the oe1 pin will disable both se1 and se2 outputs. the disable and enable of the outputs to a known state is glitch free. i2c address pin this pin sets the lsb of the i2c address. for example, if the i2c address is a6h, setting this pin high will set the i2c address to a7h. clkin_sel[0:1] pins these pins are used to set the input source clock between the input clock channels (crystal, clkin_2/clkin_2# or clkin_3/ clkin_3#). upon switching the input clock source, the output will not be glitch free. it is intended for the user to set this pin to a known state before the system is powered up or have the receiver address any unintended output signals when switching to a different input source clock. this pin has an internal 50 k? internal pull-up or pull-down at all times. 3.8 custom factory pre-programmed parts custom pre-programmed parts can be ordered corresponding to a specific configuration file generated using the clockbuilder pro soft- ware utility. silicon labs writes the configuration file into the device prior to shipping. use the clockbuilder pro custom part number wizard ( http://www.silabs.com/clockbuilderpro ) to quickly and easily generate a custom part number for your clockbuilder pro configu- ration file. a factory pre-programmed part will generate clocks at power-up. in less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your designs configuration. once you receive the confirmation email with the data sheet addendum, simply place an order with your local silicon labs sales representative. samples of your pre-programmed device will ship within two weeks. 3.9 i2c serial interface the SI5332 is fully compliant to rev6 of the i2c specification, including standard, fast, and fast+ modes. configuration and operation of the SI5332 can be controlled by reading and writing registers using the i 2 c . communication with a 1.8 v to 3.3 v host is supported. see the SI5332 family reference manual for details. 3.10 in-circuit programming the SI5332 is fully configurable using the i 2 c serial interface. at power-up the device downloads its default register values from internal non-volatile memory (nvm). refer to the SI5332 family reference manual for a detailed procedure for writing registers to volatile mem- ory. SI5332 data sheet functional description silabs.com | building a more connected world. rev. 0.7 | 19 4. register map refer to the SI5332 family reference manual for a complete list of registers descriptions and settings. SI5332 data sheet register map silabs.com | building a more connected world. rev. 0.7 | 20 5. electrical specifications table 5.1. recommended operating conditions (v dd = v dda = 1.8 v to 3.3 v +10%/-5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c) parameter symbol test condition min typ max units ambient temperature t a C40 25 85 c junction temperature tj max 125 c core supply voltage v dda , v dd_dig , v dd_xtal 1.71 3.63 v output driver supply voltage v ddo 1.425 3.63 v note: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical val- ues apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 21 table 5.2. dc characteristics (v dd = v dda = 1.8 v to 3.3 v +10%/-5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c) parameter symbol test condition min typ max units core supply current i dd 45 70 ma output buffer supply cur- rent i ddox lvpecl output 4 @ 156.25 mhz 33 35 ma hcsl output 4 @ 100 mhz 20 22 ma lvds output 4 @ 156.25 mhz 11 13 ma 3.3 v vddo lvcmos 5 output @ 170 mhz 16 19 ma 2.5 v vddo lvcmos 5 output @ 170 mhz 8 10 ma 1.8 vddo lvcmos 5 output @ 170 mhz 6 7 ma total power dissipation p d 48-pin notes 1, 6 540 mw 40-pin note 2, 6 265 mw 32-pin notes 3, 6 230 mw notes: 1. SI5332 48-pin test configuration: v ddd = v dda = v ddi = 1.8 v, 3 2.5 v lvds outputs enabled @156.25 mhz, 4x 1.8v hcsl outputs enabled @ 100 mhz, 3x 2.5 v lvpecl outputs enabled @ 125 mhz, 2x 3.3 v lvcmos outputs enabled @ 25 mhz. excludes power in termination resistors. 2. SI5332 40-pin test configuration: v ddd = v dda = v ddi = 1.8 v, 4 2.5 v lvds outputs enabled @ 156.25 mhz, 2 1.8 v hcsl outputs enabled @ 100 mhz, 2x 3.3 v lvcmos outputs enabled @ 25 mhz. . excludes power in termination resistors. 3. SI5332 32-pin test configuration: v ddd = v dda = v ddi = 1.8 v, 2 2.5 v lvds outputs enabled @ 156.25 mhz, 2 1.8 v hcsl outputs enabled @ 100 mhz. 2x 3.3 v lvcmos outputs enabled @ 25 mhz. excludes power in termination resistors. 4. differential outputs terminated into a 100 load. 5. lvcmos outputs measured into a 5 inch 50 pcb trace with 4 pf load. 50 50 100 out out i ddo differential output test configuration 5 inch 50 outa i ddo 4 pf lvcmos output test configuration 5 inch outb 6. detailed power consumption for any configuration can be estimated using clockbuilderpro when an evaluation board (evb) is not available. all evbs support detailed current measurements for any configuration. SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 22 table 5.3. clock input specifications (v dd = v dda = 1.8 v to 3.3 v +10%/-5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c) parameter symbol test condition min typ max units input clock (ac-coupled differential input clock on clkin_2/clkin_2# or clkin_3/clkin_3#) frequency f in differential 10 250 mhz voltage swing v pp differential ac-coupled < 312.5 mhz 0.5 1.8 v pp_diff slew rate sr/sf 20-80% 0.75 v/ns duty cycle dc 40 60 % input impedance r in 10 k? input capacitance c in 2 3.5 6 pf input clock (dc-coupled lvcmos input clock on clkin_2 or clkin_3) frequency f in 10 170 mhz input high voltage v ih 0.8 v dd v input low voltage v il 0.2 v dd v slew rate 1, 2 sr/sf 20-80% 0.75 v/ns duty cycle dc 40 60 % input capacitance c in 2 3.5 6 pf input clock (dc-coupled lvcmos input clock on clkin_1) frequency f in 10 170 mhz voltage swing 1 v input low voltage v il 0.2 x v dd v slew rate 1, 2 sr/sf 20-80% 0.75 v/ns duty cycle dc 40 60 % input capacitance c in 2 3.5 6 pf notes: 1. imposed for jitter performance. 2. rise and fall times can be estimated using the following simplified equation: tr/tf 80-20 = ((0.8 - 0.2) * v in_vpp_se ) / sr. SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 23 table 5.4. external crystal input specification (v dd = v dda = 1.8 v to 3.3 v +10%/-5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c) parameter symbol test condition min typ max units crystal frequency f xtal 16-50 mhz load capacitance c l 16 - 30 mhz 6 12 18 pf 31 - 50 mhz 10 pf shunt capacitance c o 16 - 30 mhz 7 pf 31 - 50 mhz 2 pf esr c l 16 - 30 mhz 50 ? 31 - 50 mhz 50 ? max crystal drive level d l 250 w input capacitance 1 c in internal cap disabled 2.5 pf internal cap enabled (per pad) 12 24 pf input voltage v xin -0.3 1.3 v notes: 1. internal capacitance on the xtal input pads is programmable or can be disabled. please reference section 5.3.1 for more detailed information. table 5.5. embedded crystal specifications parameter symbol test condition min typ max units initial accuracy fi measured at +25 c at time of shipping 20 ppm total stability C50 50 ppm temperature stability C30 30 ppm SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 24 table 5.6. control pins (v dd = v dda = 1.8 v to 3.3 v +10%/-5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c) parameter symbol test condition min typ max units SI5332 control input pins (inputx) input voltage v il -0.1 0.3 v ddox v v ih 0.7 v ddox 1 1.1 v dd v input capacitance c in 4 pf pull-up/down resistance r in 50 k note: 1. in the 48-qfn package, all universal input pins are powered by vdd_dig. 2. in the 40-qfn package, universal input4, input5, input6, and input7 on pins 21, 22, 29, 30 are powered by vddob. all other universal inputx pins are powered by vdd_dig. 3. in the 32-pin package, universal input2 and input3 on pins 23, 24 are powered by vddob. all other universal inputx pins are powered by vdd_dig. 4. if an output pair is instead defined as universal input pins in clockbuilder pro, those pins will be powered by the corresponding vddox of that corresponding bank. SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 25 table 5.7. differential clock output specifications (v dd = v dda = 1.8 v to 3.3 v +10%/-5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c) parameter symbol test condition min typ max units output frequency f out integer synthesis mode 5 312.5 mhz fractional synthesis mode 5 250 mhz duty cycle dc 48 52 % output-output skew t sk within the same bank 30 ps across banks 80 ps output voltage swing v sepp lvpecl 0.6 0.75 0.85 v pp lvds 1.8/2.5/3.3 v 0.3 0.375 0.45 v pp hcsl 0.7 0.8 0.9 v pp common mode voltage v cm lvpecl vddo-1.4 v lvds 2.5/3.3 v 1.125 1.2 1.275 v lvds 1.8 v 0.75 0.8 0.85 v hcsl 0.35 0.4 0.45 v hcsl edge rate edgr notes 12,14,18 1 4.5 v/ns hcsl delta tr d tr notes 14, 17, 18 125 ps hcsl delta tf d tf notes 14, 17, 18 125 ps hcsl vcross abs v xa notes 11, 13, 14, 17 250 550 mv hcsl vcross rel v xr notes 14, 16, 17, 24 calc calc hcsl delta vcross d vcrs notes 14, 17, 25 140 mv hcsl vovs v ovs notes 14, 17, 22 v high +300 mv hcsl vuds v uds notes 14, 17, 23 v low -300 mv hcsl vrng v rng notes 14, 17 v high -200 v low +200 mv rise and fall times (20% to 80%) t r /t f lvds 3.3 v or 2.5 v 200 350 ps 1.8 v 225 350 ps rise and fall times (20% to 80%) t r /t f lvpecl 300 ps hcsl 350 ps SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 26 parameter symbol test condition min typ max units notes: 1. for best jitter performance, keep the midpoint differential input slew rate faster than 0.3 v/ns. 2. not in pll bypass mode. 3. for best jitter performance, keep the midpoint input single ended slew rate faster than 1 v/ns. 4. on chip termination resistance can be programmed on (100ohm) or off (high impedance). 5. not including r divider. 6. input capacitance on crystal pins targets 23 pf each plus 1 pf external trace capacitance to provide 12 pf series equivalent crystal load capacitance. 7. measured at crossing point where the instantaneous voltage value of the rising edge of clk equals the falling edge of clk#. 8. measure taken from differential waveform on a component test board. the edge (slew) rate is measured from -150mv to +150mv on the differential waveform . scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge only valid for rising clock and falling clock#. signal must be monotonic through the vol to voh region for trise and tfall. 9. this measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. 10. test configuration is rs=33.2 , rp=49.9, 2 pf. 11. vcross(rel) min and max are derived using the following, vcross(rel) min = 0.250 + 0.5 (vhavg - 0.700), vcross(rel) max = 0.550 - 0.5 (0.700 C vhavg). 12. measurement taken from single ended waveform. 13. measurement taken from differential waveform vlow math function. 14. overshoot is defined as the absolute value of the maximum voltage. 15. undershoot is defined as the absolute value of the minimum voltage. 16. the crossing point must meet the absolute and relative crossing point specifications simultaneously. 17. vcross is defined as the total variation of all crossing voltages of rising clock and falling clock#. this is the maximum allowed variance in vcross for any particular system. 18. measured with oscilloscope, averaging off, using min max statistics. variation is the delta between min and max. outx outx vpp_se vpp_se vpp_diff = 2*vpp_se vcm vcm vcm 19. lvds swing levels for 50 ? transmission lines. SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 27 table 5.8. lvcmos clock output specifications (v dd = v dda = 1.8 v to 3.3 v +10%/-5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c) parameter symbol test condition min typ max units frequency fout 1.8-3.3 v cmos 5 170 mhz 1.5 v cmos 5 133.33 mhz rise/fall time, 3.3 v (20-80%) t r /t f 50 ? impedance, 5 trace, cl = 4 pf 0.5 0.8 ns rise/fall time, 2.5 v (20-80%) t r /t f 50 ? impedance, 5 trace cl = 4 pf 0.6 0.9 ns rise/fall time, 1.8 v (20-80%) t r /t f 50 ? impedance, 5 trace cl = 4 pf 0.75 1.1 ns rise/fall time, 1.5 v (20-80%) t r /t f 50 ? impedance, 5 trace cl = 4 pf 0.9 1.2 ns cmos output resistance (single strength) 3.3 v 46 ? 2.5 v 48 ? 1.8 v 53 ? 1.5 v 58 ? cmos output resistance (double strength) 3.3 v 23 ? 2.5 v 24 ? 1.8 v 27 ? 1.5 v 29 ? cmos output voltage v oh C4 ma load vddo-0.3 v v ol 4 ma load 0.3 v duty cycle dc xo and pll mode 45 55 % SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 28 table 5.9. performance characteristics (v dd = v dda = 1.8 v to 3.3 v +10%/-5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c) parameter symbol test condition min typ max units power ramp t vdd 0 v to v ddmin 0.1 10 ms initialization time t initialization time for i2c to become operational after core supply exceeds v ddmin 15 ms clock stabilization from power-up t stable time for clock outputs to appear after por 15 25 ms input to output propagation delay t prop buffer mode (pll bypass) 2.5 4 ns spread spectrum pp frequency deviation ssdev multisynth output < 250 mhz 0.1 2.5 % 0.5% spread frequency deviation ssdev multisynth output < 250 mhz 0.4 0.45 0.5 % spread spectrum modulation rate ssdev multisynth output < 250 mhz 30 31.5 33 khz notes: 1. outputs at same frequencies and using the same driver format. 2. the maximum step size is only limited by the register lengths; however, the multisynth output frequency must be kept between 5 mhz and 250mhz. 3. update rate via i2c is also limited by the time it takes to perform a write operation. 4. default value is ~31.5 khz. SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 29 table 5.10. jitter performance specifications (v dd = v dda = 1.8 v to 3.3 v +10%/-5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c) parameter symbol test condition typ max units jitter generation, locked to external 25 mhz clock j gen int mode 12 khz C 20 mhz 1,2 230 280 fs rms frac/dco mode 12 khz C 20 mhz 3,5 500 fs rms j per derived from integrated phase noise at a ber of 1e-12 3.3 ps pk-pk j cc 3.1 ps pk j per n = 10, 000 cycles integer or fractional mode. 2,3 measured in the time domain. performance is limited by the noise floor of the equipment. 12 ps pk-pk j cc 11 ps pk jitter generation, locked to external 25 mhz crystal j gen int mode 12 khz C 20 mhz 1,2 230 280 fs rms frac/dco mode 12 khz C 20 mhz 3,5 500 fs rms j per derived from integrated phase noise at a ber of 1e-12 3.5 ps pk-pk j cc 3.1 ps pk j per n = 10, 000 cycles integer or fractional mode. 2,3 measured in the time domain. performance is limited by the noise floor of the equipment. 12 ps pk-pk j cc 11 ps pk jitter generation, locked to embedded 50 mhz crystal j gen int mode 12 khz C 20 mhz 1,2 230 fs rms frac/dco mode 12 khz C 20 mhz 3,5 500 fs rms j per derived from integrated phase noise at a ber of 1e-1 3.5 ps pk-pk j cc 3.1 ps pk j per n = 10, 000 cycles integer or fractional mode. 2,3 measured in the time domain. performance is limited by the noise floor of the equipment. 12 ps pk-pk j cc 11 ps pk power supply noise rejection 6 psnr 25 khz C100 dbc 50 khz C97 100 khz C72 500 khz C83 1 mhz -91 SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 30 parameter symbol test condition typ max units notes: 1. int jitter generation test conditions f out = 156.25 mhz lvpecl. 2. integer mode assumes that the output dividers (nn/nd) are configured with an integer value. 3. fractional and dco modes assume that the output dividers (nn/nd) are configured with a fractional value and the feedback divid- er is integer. 4. all jitter data in this table is based upon all output formats being differential. when lvcmos outputs are used, there is the poten- tial that the output jitter may increase due to the nature of lvcmos outputs. if your configuration implements any lvcmos out- put and any output is required to have jitter less than 3 ps rms, contact silicon labs for support to validate your configuration and ensure the best jitter performance. 5. frac jitter generation test conditions f out = 150 mhz lvpecl. 6. measured at 156.25 mhz carrier frequency. 100 mvpp sine wave noise added and noise spur amplitude measured. SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 31 table 5.11. pci-express clock outputs (100 mhz hcsl) (v dd = v dda = 1.8 v to 3.3 v +10%/-5%, v ddo = 1.8 v 5%, 2.5 v 5%, or 3.3 v 5%, t a = C40 to 85 c) parameter test condition ssc on/off typ max units pcie gen 1.1 includes pll bw 1.5C22 mhz, peaking = 3db, td=10 ns, ftrk=1.5 mhz with ber = 1e-12 2 off 11 17 ps rms on 22 30 ps rms pcie gen 2.1 includes pll bw 5mhz & 8C16 mhz, jitter peaking = 0.01-1 db & 3 db, td=12ns, low band, f < 1.5 mhz off 0.12 0.16 ps rms on 0.8 1.2 ps rms includes pll bw 5 mhz & 8C16 mhz, jitter peaking = 0.01-1db & 3db, td=12ns, high band, 1.5 mhz < f < nyquist 2 off 0.016 0.02 ps rms on 0.12 0.2 ps rms pcie gen 3.0 com- mon clock includes pll bw 2C4 mhz & 5 mhz, peaking = 0.01-2db & 1db, td=12 ns, cdr = 10 mhz 2, 3 off 0.037 0.047 ps rms on 0.26 0.32 ps rms pcie gen3.0 sris includes pll bw 4 mhz peaking = 2db & 1db, td=12 ns cdr = 10 mhz 2, 3 on 0.35 0.38 ps rms pcie gen 4.0 com- mon clock includes pll bw 2C4 mhz & 5 mhz, peaking = 0.01-2db & 1db, td=12 ns, cdr = 10 mhz 2, 3 off 0.037 0.047 ps rms on 0.26 0.32 ps rms pcie gen4.0 sris includes pll bw 4 mhz peaking = 2db & 1db, td=12 ns cdr = 10 mhz 2, 3 on 0.37 0.4 ps rms notes: 1. all jitter data in this table is based upon all output formats being differential. when lvcmos outputs are used, there is the poten- tial that the output jitter may increase due to the nature of lvcmos outputs. if your configuration implements any lvcmos out- put and any output is required to have jitter less than 3 ps rms, contact silicon labs for support to validate your configuration and ensure the best jitter performance. 2. all output clocks 100 mhz hcsl format. jitter data taken from clock jitter tool v.1.3. 3. excludes oscilloscope sampling noise. SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 32 table 5.12. thermal characteristics (SI5332a/b/c/d only) parameter symbol test condition 1 value units SI5332 48 qfn thermal resistance, junction to ambient ja still air 25.5 c/w air flow 1 m/s 22.1 air flow 2 m/s 20.9 thermal resistance, junction to case jc 14 thermal resistance, junction to board jb 11.3 jb 11.0 thermal resistance, junction to top center jt 0.4 SI5332 40 qfn thermal resistance, junction to ambient ja still air 25.6 c/w air flow 1 m/s 22.2 air flow 2 m/s 21.0 thermal resistance, junction to case jc 14.1 thermal resistance, junction to board jb 11.4 jb 11.1 thermal resistance, junction to top center jt 0.4 SI5332 32 qfn thermal resistance, junction to ambient ja still air 32.8 c/w air flow 1 m/s 28.8 air flow 2 m/s 27.6 thermal resistance, junction to case jc 18.5 thermal resistance, junction to board jb 15.1 jb 14.9 thermal resistance, junction to top center jt 0.5 note: 1. based on pcb dimension: 3 x 4.5, pcb thickness: 1.6 mm, pcb land/via under gnd pad: 36, number of cu layers: 4. 2. thermal characteristics for SI5332e/f/g/h for embedded crystal package options will be available soon. SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 33 table 5.13. absolute maximum ratings 1,2,3 parameter symbol test condition value units storage temperature range t stg C55 to +150 c dc supply voltage v dd C0.5 to 3.8 v v dda C0.5 to 3.8 v vdd xtal C0.5 to 3.8 v v ddo C0.5 to 3.8 v input voltage range v i xin/xout C0.3 to 1.3 v latch-up tolerance lu jesd78 compliant esd tolerance hbm 100 pf, 1.5 k 2.0 kv junction temperature t jct C55 to 125 c soldering temperature (pb-free profile) t peak 260 c soldering temperature time at t peak (pb-free profile) t p 20 to 40 sec notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. 2. for more packaging information, go to www.silabs.com/support/quality/pages/rohsinformation.aspx . 3. the device is compliant with jedec j-std-020. SI5332 data sheet electrical specifications silabs.com | building a more connected world. rev. 0.7 | 34 6. pin descriptions 6.1 pin descriptions (48-qfn) input1 out10 out10b xa/clkin1 xb vdd_xtal vdd_dig vddo5 out11 out11b input6 out9 1 2 3 4 5 6 7 8 48 47 46 45 44 43 42 41 out7b out7 9 10 11 12 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 out9b vddo4 vddo3 49 gnd input2 input3 clkin_2 clkin_2b vdda input5 out6b out6 out5b out5 out4b out4 out3b out3 out1b out1 vddo0 out0b out0 input4 sclk sdata clkin_3 clkin_3b vddo1 out2b out2 vddo2 out8b out8 input7 figure 6.1. 48-qfn SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 35 table 6.1. SI5332 pin descriptions (48-qfn) pin number pin name pin type function 1 vdd_dig p voltage supply for digital functions. connect to 1.8C3.3 v. 2 clkin_2 i these pins accept both differential and single-ended clock signals. refer to section 3.4.2 input clocks for input termination options. these pins are high-impedance and must be terminated externally. if both the clkin_2 and clkin_2b inputs are un-used and powered down, then both inputs can be left floating. clockbuilder pro will power down an input that is set as "un- used". 3 clkin_2b i 4 vdd_xtal p voltage supply for crystal oscillator. connect to 1.8C3.3 v. 5 xa/clkin1 i or p SI5332a/b/c/d: these pins are used for an optional xtal input when operating the device in asynchronous mode (i.e. free-run mode). alternatively, an external lvcmos reference clock (refclk) can be applied to pin 5. refer to sec- tion 5. electrical specifications for recommended crystal specifications. SI5332e/f/g/h (embedded crystal) no connect. do not connect pins 5 or 6 to anything. 6 xb i or p 7 clkin_3 i these pins accept both differential and single-ended clock signals. refer to section 3.4.2 input clocks for input termination options. these pins are high-impedance and must be terminated externally. if both the clkin_3 and clkin_3b inputs are un-used and powered down, then both inputs can be left floating. clockbuilder pro will power down an input that is set as "un- used". 8 clkin_3b i 9 vdda p core supply voltage. connect to 1.8C3.3 v. see the SI5332 family reference manual for power supply filtering recom- mendations. 10 input1 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to section 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 11 input2 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to section 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 12 input3 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to section 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 13 sclk i serial clock input this pin functions as the serial clock input for i 2 c. 14 sda i/o serial data interface this is the bidirectional data pin (sda) for the i 2 c mode. 15 out0b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 16 out0 o SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 36 pin number pin name pin type function 17 vddo0 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out0 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 18 out1b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 19 out1 o 20 vddo1 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out1 and out2 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 21 out2b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 22 out2 o 23 input4 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to section 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 24 vddo2 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out3, out4, and out5 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 25 out3b o output clock these output clocks support a programmable signal swing & common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output ter- minations and 3.5.3 lvcmos output terminations. unused outputs should be left unconnected. 26 out3 o 27 out4b o output clock these output clocks support a programmable signal swing & common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output ter- minations and 3.5.3 lvcmos output terminations. unused outputs should be left unconnected. 28 out4 o SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 37 pin number pin name pin type function 29 out5b o output clock these output clocks support a programmable signal swing & common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output ter- minations and 3.5.3 lvcmos output terminations. unused outputs should be left unconnected. 30 out5 o 31 out6b o output clock these output clocks support a programmable signal swing & common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output ter- minations and 3.5.3 lvcmos output terminations. unused outputs should be left unconnected. 32 out6 o 33 out7b o output clock these output clocks support a programmable signal swing & common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output ter- minations and 3.5.3 lvcmos output terminations. unused outputs should be left unconnected. 34 out7 o 35 out8b o output clock these output clocks support a programmable signal swing & common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output ter- minations and 3.5.3 lvcmos output terminations. unused outputs should be left unconnected. 36 out8 o 37 vddo3 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out6, out7, and out8 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 38 input5 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 39 vddo4 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out9 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 40 out9b o output clock these output clocks support a programmable signal swing & common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output ter- minations and 3.5.3 lvcmos output terminations. unused outputs should be left unconnected. 41 out9 o 42 input6 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 38 pin number pin name pin type function 43 input7 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 44 vddo5 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out10 and out11 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 45 out10b o output clock these output clocks support a programmable signal swing & common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output ter- minations and 3.5.3 lvcmos output terminations. unused outputs should be left unconnected. 46 out10 o 47 out11b o output clock these output clocks support a programmable signal swing & common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output ter- minations and 3.5.3 lvcmos output terminations. unused outputs should be left unconnected. 48 out11 o 49 gnd pad p ground pad this pad provides electrical and thermal connection to ground and must be connected for proper operation. SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 39 6.2 pin descriptions (40-qfn) 41 ground 11 12 13 14 15 16 40 39 38 37 36 35 34 33 18 19 20 31 32 17 21 22 23 24 25 26 27 28 29 30 vddo1 out1b out1 vddo0 out0b out0 sclk sdata input1 xa/clkin1 xb vdd_xtal clkin_2 clkin_2b vdda vdd_dig vddo5 input6 out7 out7b vddo4 out6 out6b input4 input5 vddo2 input2 input3 out3b out3 out2b out2 vddo3 2 3 4 5 6 7 8 9 10 1 clkin_3 clkin_3b out4b out4 out5b out5 input7 figure 6.2. 40-qfn SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 40 table 6.2. SI5332 pin descriptions (40-qfn) pin number pin name pin type function 1 vdd_dig p voltage supply for digital functions. connect to 1.8C3.3 v. 2 clkin_2 i these pins accept both differential and single-ended clock signals. refer to section 3.4.2 input clocks for input termination options. these pins are high-impedance and must be terminated externally. if both the clkin_2 and clkin_2b inputs are un-used and powered down, then both inputs can be left floating. clockbuilder pro will power down an input that is set as "un- used". 3 clkin_2b i 4 vdd_xtal p voltage supply for crystal oscillator. connect to 1.8C3.3 v. 5 xa/clkin1 i or p SI5332a/b/c/d: these pins are used for an optional xtal input when operating the device in asynchronous mode (i.e. free-run mode). alternatively, an external lvcmos reference clock (refclk) can be applied to pin5. refer to sec- tion 5. electrical specifications for recommended crystal specifications. SI5332e/f/g/h (embedded crystal) no connect. do not connect pins 5 or 6 to anything. 6 xb i or p 7 clkin_3 i these pins accept both differential and single-ended clock signals. refer to section 3.4.2 input clocks for input termination options. these pins are high-impedance and must be terminated externally. if both the clkin_3 and clkin_3b inputs are un-used and powered down, then both inputs can be left floating. clockbuilder pro will power down an input that is set as "un- used". 8 clkin_3b i 9 vdda p core supply voltage. connect to 1.8C3.3 v. see the SI5332 family reference manual for power supply filtering recom- mendations. 10 input1 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to section 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 11 sclk i serial clock input this pin functions as the serial clock input for i 2 c. 12 sda i/o serial data interface this is the bidirectional data pin (sda) for the i 2 c mode. 13 out0b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 14 out0 o 15 vddo0 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out0 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 41 pin number pin name pin type function 16 out1b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 17 out1 o 18 vddo1 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out1 and out2 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 19 input2 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 20 input3 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 21 out2b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 22 out2 o 23 out3b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 24 out3 o 25 vddo2 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out3, out4, and out5 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 26 out4b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 27 out4 o 28 vddo3 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out6, out7, and out8 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 42 pin number pin name pin type function 29 out5b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 30 out5 o 31 input4 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 32 input5 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 33 vddo4 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out9 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 34 out6b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 35 out6 o 36 input6 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 37 input7 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 38 out7b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 39 out7 o 40 vddo5 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out10 and out11 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 41 gnd pad p ground pad this pad provides electrical and thermal connection to ground and must be connected for proper operation. SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 43 6.3 pin descriptions (32-qfn) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 30 29 28 27 26 25 24 23 22 21 20 19 7 8 18 17 32 31 33 gnd xa/clkin1 xb vdd_xtal input1 clkin_2 clkin_2b vdda vddo1 out1b vddo0 out0b out0 sclk sdata vdd_dig vddo5 out5 out5b vddo4 out4 out4b vddo3 input3 out3b out3 out2b out2 vddo2 input5 input4 out1 input2 figure 6.3. 32-qfn table 6.3. SI5332 pin descriptions, (32-qfn) pin number pin name pin type function 1 vdd_dig p voltage supply for digital functions. connect to 1.8C3.3 v. 2 clkin_2 i these pins accept both differential and single-ended clock signals. refer to section 3.4.2 input clocks for input termination options. these pins are high-impedance and must be terminated externally. if both the clkin_2 and clkin_2b inputs are un-used and powered down, then both inputs can be left floating. clockbuilder pro will power down an input that is set as "un- used". 3 clkin_2b i 4 vdd_xtal p voltage supply for crystal oscillator. connect to 1.8C3.3 v. 5 xa/clkin1 i or p SI5332a/b/c/d these pins are used for an optional xtal input when operating the device in asynchronous mode (i.e. free-run mode). alternatively, an external lvcmos reference clock (refclk) can be applied to pin 5. refer to sec- tion 5. electrical specifications for recommended crystal specifications. SI5332e/f/g/h (embedded crystal) no connect. do not connect these pins 5 or 6 to anything. 6 xb i or p SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 44 pin number pin name pin type function 7 vdda p core supply voltage. connect to 1.8C3.3 v. see the SI5332 family reference manual for power supply filtering recom- mendations. 8 input1 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to section 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 9 sclk i serial clock input this pin functions as the serial clock input for i 2 c. 10 sda i/o serial data interface this is the bidirectional data pin (sda) for the i 2 c mode. 11 out0b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 12 out0 o 13 vddo0 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out0 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 14 out1b o output clock these output clocks support a programmable signal swing & common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output ter- minations and 3.5.3 lvcmos output terminations. unused outputs should be left unconnected. 15 out1 o 16 vddo1 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out1 and out2 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 17 input2 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to section 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 18 out2b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 19 out2 o SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 45 pin number pin name pin type function 20 vddo2 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out3, out4, and out5 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 21 out3b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 22 out3 o 23 vddo3 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out6, out7, and out8 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 24 input3 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to section 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 25 vddo4 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out9 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 26 out4b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 27 out4 o 28 input4 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to section 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 29 input5 i universal hw input pin. this hardware input pin is user definable through clockbuilder pro. refer to section 3.7 universal hardware input pins for a list of definitions that hardware input pins can be used for. 30 out5b o output clock these output clocks support a programmable signal swing and common mode voltage. desired output signal format is configurable using register control. termination recommendations are provided in 3.5.2 differential output terminations and 3.5.3 lvcmos output terminations . unused out- puts should be left unconnected. 31 out5 o SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 46 pin number pin name pin type function 32 vddo5 p supply voltage (1.8C3.3 v, or 1.5 v for cmos only) for out10 and out11 see the SI5332 family reference manual for power supply filtering recom- mendations. leave vddox pins of unused output drivers unconnected. an alternate op- tion is to connect the vddox pin to a power supply and disable the output driver to minimize current consumption. 33 gnd pad p ground pad this pad provides electrical and thermal connection to ground and must be connected for proper operation. SI5332 data sheet pin descriptions silabs.com | building a more connected world. rev. 0.7 | 47 7. package outline 7.1 SI5332 6x6 mm 48-qfn package diagram, external crystal versions (SI5332a/b/c/d) the figure below illustrates the package details for the SI5332a/b/c/d in 48-qfn. the table below lists the values for the dimensions shown in the illustration. figure 7.1. 48-pin quad flat no-lead (qfn) table 7.1. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.15 0.20 0.25 d 6.00 bsc d2 3.50 3.60 3.70 e 0.40 bsc e 6.00 bsc e2 3.50 3.60 3.70 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.10 eee 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5332 data sheet package outline silabs.com | building a more connected world. rev. 0.7 | 48 7.2 SI5332 6x6 mm 40-qfn package diagram, external crystal versions (SI5332a/b/c/d) the figure below illustrates the package details for the SI5332a/b/c/d in 40-qfn. the table below lists the values for the dimensions shown in the illustration. figure 7.2. 40-pin quad flat no-lead (qfn) table 7.2. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.20 0.25 d 6.00 bsc d2 4.35 4.50 4.65 e 0.50 bsc e 6.00 bsc e2 4.35 4.50 4.65 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5332 data sheet package outline silabs.com | building a more connected world. rev. 0.7 | 49 7.3 SI5332 5x5 mm 32-qfn package diagram, external crystal versions (SI5332a/b/c/d) the figure below illustrates the package details for the SI5332a/b/c/d 32-qfn option. the table below lists the values for the dimen- sions shown in the illustration. figure 7.3. 32-pin quad flat no-lead (qfn) table 7.3. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 5.00 bsc d2 2.85 3.00 3.15 e 0.50 bsc e 5.00 bsc e2 2.85 3.00 3.15 l 0.30 0.40 0.50 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.10 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5332 data sheet package outline silabs.com | building a more connected world. rev. 0.7 | 50 7.4 SI5332 6x6 mm 48-qfn package diagram, embedded crystal versions (SI5332e/f/g/h) the figure below illustrates the package details for the SI5332e/f/g/h in 48-qfn. the table below lists the values for the dimensions shown in the illustration. figure 7.4. 48-pin quad flat no-lead (qfn) table 7.4. package dimensions dimension min nom max a 0.90 1.0 1.1 a1 0.26 ref a2 0.70 ref b 0.18 0.23 0.28 d 6.00 bsc d2 2.5 ref e 6.00 bsc e2 2.5 ref e 0.40 bsc l 0.30 0.35 0.40 l1 0.10 ref aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.01 eee 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5332 data sheet package outline silabs.com | building a more connected world. rev. 0.7 | 51 7.5 SI5332 6x6 mm 40-qfn package diagram, embedded crystal versions (SI5332e/f/g/h) the figure below illustrates the package details for the SI5332e/f/g/h in 40-qfn. the table below lists the values for the dimensions shown in the illustration. figure 7.5. 40-pin quad flat no-lead (qfn) table 7.5. package dimensions dimension min nom max a 0.90 1.0 1.1 a1 0.26 ref a2 0.70 ref b 0.18 0.23 0.28 d 6.00 bsc d2 2.5 ref e 6.00 bsc e2 2.5 ref e 0.50 bsc. l 0.30 0.35 0.40 l1 0.10 ref aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.01 eee 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5332 data sheet package outline silabs.com | building a more connected world. rev. 0.7 | 52 7.6 SI5332 5x5 mm 32-qfn package diagram, embedded crystal versions (SI5332e/f/g/h) the figure below illustrates the package details for the SI5332e/f/g/h 32-qfn option. the table below lists the values for the dimen- sions shown in the illustration. figure 7.6. 32-pin quad flat no-lead (qfn) table 7.6. package dimensions dimension min nom max a 0.90 1.0 1.1 a1 0.26 ref a2 0.70 ref b 0.2 0.25 0.30 d 5.00 bsc d2 2.1 ref e 5.00 bsc e2 2.1 ref e 0.50 bsc l 0.32 0.37 0.42 l1 0.10 ref aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.01 eee 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5332 data sheet package outline silabs.com | building a more connected world. rev. 0.7 | 53 8. pcb land pattern 8.1 SI5332 48-qfn land pattern figure 8.1. 48-qfn land pattern table 8.1. pcb land pattern dimensions dimension mm c1 5.52 c2 5.52 e 0.40 bsc x1 0.20 y1 0.50 x2 2.60 y2 2.60 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads. 4. a 33 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5332 data sheet pcb land pattern silabs.com | building a more connected world. rev. 0.7 | 54 8.2 SI5332 40-qfn land pattern figure 8.2. 40-qfn land pattern table 8.2. pcb land pattern dimensions dimension mm c1 5.52 c2 5.52 e 0.50 bsc x1 0.30 y1 0.50 x2 2.60 y2 2.60 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads. 4. a 33 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5332 data sheet pcb land pattern silabs.com | building a more connected world. rev. 0.7 | 55 8.3 SI5332 32-qfn land pattern the figure below illustrates the pcb land pattern details for SI5332 in 32-qfn package. the table below lists the values for the dimen- sions shown in the illustration. figure 8.3. 32-qfn land pattern table 8.3. pcb land pattern dimensions dimension mm c1 4.5 c2 4.5 e 0.50 x1 0.30 y1 0.45 x2 3.15 y2 3.15 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads. 4. a 33 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. SI5332 data sheet pcb land pattern silabs.com | building a more connected world. rev. 0.7 | 56 9. top marking SI5332g r-gmp t t t t t t y y w w SI5332g rxxxxx t t t t t t y y w w standard factory default configuration custom, factory pre-programmed configurations figure 9.1. SI5332 top marking table 9.1. top marking explanation line characters description 1 SI5332g base part number and device grade g = device grade (a, b, c, d, e, f, g, h) 2 r-gmp r = product revision (see ordering guide for current revision) - = dash character gm = package (qfn) and temperature range (-40 to +85c) p = package size ? 1 = 6-output, 32-pin qfn ? 2 = 8-output, 40-pin qfn ? 3 = 12-output, 48-pin qfn rxxxxx r = product revision (see ordering guide for current revision) xxxxx = customer specific nvm sequence number. nvm code assigned for custom, factory pre-programmed devices using clockbuilder pro. see ordering guide for more information. 3 tttttt manufacturing trace code. 4 yyww year (yy) and work week (ww) of package assembly SI5332 data sheet top marking silabs.com | building a more connected world. rev. 0.7 | 57 10. document change list 10.1 revision 0.7 september 6, 2017 ? initial release. SI5332 data sheet document change list silabs.com | building a more connected world. rev. 0.7 | 58 http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa clockbuilder pro one-click access to timing tools, documentation, software, source code libraries & more. available for windows and ios (cbgo only). www.silabs.com/cbpro timing portfolio www.silabs.com/timing sw/hw www.silabs.com/cbpro quality www.silabs.com/quality support and community community.silabs.com disclaimer silicon labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon labs products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon labs shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products are not designed or authorized to be used within any life support system without the specific written consent of silicon labs. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon labs products are not designed or authorized for military applications. silicon labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc.? , silicon laboratories?, silicon labs?, silabs? and the silicon labs logo?, bluegiga?, bluegiga logo?, clockbuilder?, cmems?, dspll?, efm?, efm32?, efr, ember?, energy micro, energy micro logo and combinations thereof, "the worlds most energy friendly microcontrollers", ember?, ezlink?, ezradio?, ezradiopro?, gecko?, isomodem?, micrium, precision32?, proslic?, simplicity studio?, siphy?, telegesis, the telegesis logo?, usbxpress?, zentri and others are trademarks or registered trademarks of silicon labs. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders. |
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